The present invention relates to microfabrication of semiconductor devices, and, more specifically, to methods for taking into account signal integrity in the automatic generation of test patterns for semiconductor devices and/or semiconductor device manufacture.
Semiconductor devices and components thereof continue to decrease in size, resulting in increasing circuit density. As a result, the effect of crosstalk defects has emerged as a factor to consider during manufacturing testing of a chip. Crosstalk faults can arise when two lines in a circuit are so close that their parasitic capacitances influence their signal states. A decrease in feature size can increase parasitic capacitance so that the effect of a crosstalk fault can become more prominent. When this coupling capacitance exceeds a certain threshold value, the state of one signal will influence the other if there are transitions on either or both lines. If there is a transition on only one line, a crosstalk glitch is produced; on the other hand, transitions on both lines result in a crosstalk delay. It should be noted that crosstalk faults are different from bridging faults, which can also arise when two lines are in close proximity. However, the cause of bridging faults is a resistive connection between the two lines and not capacitive. Also, the effects of the two faults are different: bridging faults result in wired-AND and wired-OR logic functions, thus incurring a stuck-at defect on a signal, whereas crosstalk faults result in glitch or delay.